DEVS for mixed-signal Modeling based on VHDL
نویسندگان
چکیده
We show how to build generic DEVS models to facilitate simulation of mixed signal Hardware Description Language models within a DEVS simulator. We present the models required, and the conversion procedures for a subset of VHDL called sAMS-VHLD. Hierarchical models written in sAMS-VHDL that utilize Processes, Signals and Simultaneous Statements are be simulated in the CD++ toolkit by elaborating the model, and converting the model hierarchy into an equivalent CD++ coupled model. These Process, Signal and Integrator models and their associated conversion procedures were designed and then tested in CD++ using a number of characteristic sAMS-VHDL models.
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